1. Field of the Invention
The present invention relates to a clock extraction circuit for extracting a timing clock signal from a non-return zero signal used in the field of optical communications or the like and supplying this timing clock signal to an identification reproducer for performing data reproduction.
2. Description of the Related Art
In high-speed digital communications having, for example a transmission speed of 1 [Gb/s] or higher, where data is time-division multiplexed and transmitted/received so as to separate time, a receiving section needs a clock according to a transmission speed for identifying received data or separating time. According to a conventional method, a clock component is extracted from high-speed data before time is separated and, by using this clock, identification and time separation are performed. Consequently, a clock extraction circuit operated at a high speed is necessary and processing greatly depends upon a device characteristic. Especially, in a region where data transmission speed exceeds 1 [Gb/s], it is difficult to realize a high-speed phase comparator.
The conventional clock extraction circuit shown in FIG. 1 comprises edge detecting circuit 1 for detecting the changing point of a non-return zero signal inputted from input terminal 10, phase comparator 4 for comparing, based on the output of edge detecting circuit 1 and the output signal of voltage control oscillator 7, the phase of the received non-return zero signal with that of the output signal of voltage control oscillator 7, low pass filter 6 for outputting only a signal having a specified low frequency, and voltage control oscillator 7 for oscillating a pulse signal according to a signal sent from low pass filter 6 and sending the oscillated pulse signal to output terminal 20 and phase comparator 4.
In the foregoing conventional clock extraction circuit, it is the phase comparator that always determines a speed limit for enabling a stable operation to be performed. In other words, in order to receive a non-return zero signal having a transmission speed of f [b/s], the phase comparator must be operated also at the speed of f [Hz]. However, since there is a limit to the operational speed of a currently available phase comparator, the number of phase comparators that can actually operate stably at high speeds is very small.
As apparent from the foregoing, in a communication system which uses a receiver including the conventional clock extraction circuit, there is a limit to the operational speed of the phase comparator and, consequently, the information transmission speed of the entire communication system is limited.
Some phase comparators that can operate at high speeds have been realized. However, since these are very costly and large in size, it is impossible to satisfy market requests for reduction in cost and size of the device.
Japanese unexamined Patent Publication No. 1988-7050 discloses a timing clock extraction circuit, which comprises a first frequency divider for frequency-dividing the output of a voltage control oscillator to a frequency band nearly equal to the transmission speed of an inputted signal, and a second frequency divider for frequency-dividing the output of the first frequency divider to 1/2, then the output of the second frequency divider is inputted to a phase comparator. However, this timing clock extraction circuit is disadvantageous in that, as described later, if used for detecting a non-return zero signal, its configuration may produce an error value as a phase difference.